论文标题
VVC变换块的轻巧硬件实现ASIC解码器
Lightweight hardware implementation of VVC transform block for ASIC decoder
论文作者
论文摘要
多功能视频编码（VVC）是2020年底预期的下一代视频编码标准。与其前身相比，VVC引入了新的编码工具，以使压缩更有效地以较高的计算复杂性为代价。这提出了设计高效且优化的实现的需求，尤其是对于具有有限的内存和逻辑资源的嵌入式平台。 VVC中新引入的工具之一是多转换选择（MTS）。后者涉及具有较大和矩形变换块的三个离散余弦变换（DCT）/离散的正弦变换（DST）类型。在本文中，提出了所有DCT/DST变换类型和尺寸的有效硬件实现。拟议的设计在针对ASIC平台的管道架构中使用32个乘数。它由一个多标准架构组成，该体系结构支持最近的MPEG标准的转换块，包括AVC，HEVC和VVC。优化了体系结构，并通过使用常规乘数而不是多个恒定的多层次来消除其他提出的体系结构中发现的不必要的复杂性。合成的结果表明，所提出的方法，该方法维持两个像素/循环的恒定吞吐量和所有块尺寸的恒定LA，可以达到600 MHz的操作频率，使其在48 fps中以实时4K视频进行解码。
Versatile Video Coding (VVC) is the next generation video coding standard expected by the end of 2020. Compared to its predecessor, VVC introduces new coding tools to make compression more efficient at the expense of higher computational complexity. This rises a need to design an efficient and optimised implementation especially for embedded platforms with limited memory and logic resources. One of the newly introduced tools in VVC is the Multiple Transform Selection (MTS). This latter involves three Discrete Cosine Transform (DCT)/Discrete Sine Transform (DST) types with larger and rectangular transform blocks. In this paper, an efficient hardware implementation of all DCT/DST transform types and sizes is proposed. The proposed design uses 32 multipliers in a pipelined architecture which targets an ASIC platform. It consists in a multi-standard architecture that supports the transform block of recent MPEG standards including AVC, HEVC and VVC. The architecture is optimized and removes unnecessary complexities found in other proposed architec-tures by using regular multipliers instead of multiple constant multi-pliers. The synthesized results show that the proposed method which sustain a constant throughput of two pixels/cycle and constant la-tency for all block sizes can reach an operational frequency of 600 Mhz enabling to decode in real-time 4K videos at 48 fps.
